\ud83d\udc49\ufe0f 32\ube44\ud2b8 \ubcf4\ud638\ubaa8\ub4dc\ub85c \uc804\ud658\ud558\ub294 \ubd80\ubd84\uc785\ub2c8\ub2e4. This is the part where the system switches to 32-bit protected mode.<\/p>\n\n\n\n
\ud83d\udc49\ufe0f 16\ube44\ud2b8\uc5d0\uc11c \uadf8\ub798\ud53d \ubaa8\ub4dc\ub85c \uc124\uc815\ud558\uace0 32\ube44\ud2b8 \ubcf4\ud638\ubaa8\ub4dc\ub85c \uc804\ud658\ud6c4\uc5d0 \ud654\uba74\uc5d0 \ud551\ud06c\uc0c9 \uc0ac\uac01\ud615\uc744 \uadf8\ub9ac\ub294 \ucf54\ub4dc\uc785\ub2c8\ub2e4. This code sets the system to 16-bit graphics mode, switches to 32-bit protected mode, and then draws a pink rectangle on the screen.<\/p>\n\n\n\n
\ud83d\udc49\ufe0f \uc804\uccb4 \ucf54\ub4dc \/ Full Code<\/p>\n\n\n\n
\u2714\ufe0f boot.asm<\/p>\n\n\n\n
— jmp 0x8000 \uc774 \ucf54\ub4dc\ub97c \uc544\ub798\ucc98\ub7fc \uc218\uc815\ud588\uc2b5\ub2c8\ub2e4. I modified the jmp 0x8000 code as shown below.<\/p>\n\n\n\n
— \ub098\uba38\uc9c0\ub294 \uc774 \uc804\uacfc \uac19\uc544 \uc124\uba85\uc744 \uc0dd\ub7b5\ud569\ub2c8\ub2e4. The rest is the same as before, so I will omit the explanation.<\/p>\n\n\n\n
jmp 0x0000:0x8000<\/code><\/pre>\n\n\n\n
\u2714\ufe0f sector2.asm<\/p>\n\n\n\n
[org 0x8000]\nbits 16\n\nstart:\n ; --------------------------------\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500----\n ; 1. A20 \uac8c\uc774\ud2b8 \ud65c\uc131\ud654 (\ud0a4\ubcf4\ub4dc \ucee8\ud2b8\ub864\ub7ec \uc774\uc6a9\ud55c \ud45c\uc900 \ubc29\uc2dd)\n ; 1. Enable A20 Gate (Standard method using keyboard controller)\n ; --------------------------------\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500----\n in al, 0x92\n or al, 2\n out 0x92, al\n\n ; ----------------------------------------------------\n ; 2. GDT(Global Descriptor Table) \uc815\ubcf4\ub97c CPU\uc5d0 \ub85c\ub4dc\n ; 2. Load GDT (Global Descriptor Table) information into CPU\n ; ----------------------------------------------------\n cli ; 32\ube44\ud2b8 \uc804\ud658 \uc911 \ubc29\ud574\ubc1b\uc9c0 \uc54a\ub3c4\ub85d \ud558\ub4dc\uc6e8\uc5b4 \uc778\ud130\ub7fd\ud2b8 \uae08\uc9c0\n ; Disable hardware interrupts to avoid interruption during 32-bit transition\n lgdt [gdt_pointer] ; GDT \uad6c\uc870\uccb4\uc758 \uc8fc\uc18c\ub97c CPU\uc5d0 \ub85c\ub4dc\n ; Load the address of the GDT structure into the CPU\n\n ; ----------------------------------------------------\n ; 3. CR0 \ub808\uc9c0\uc2a4\ud130\ub97c \uc124\uc815\ud558\uc5ec 32\ube44\ud2b8 \ubcf4\ud638 \ubaa8\ub4dc \ud65c\uc131\ud654\n ; 3. Set CR0 register to enable 32-bit Protected Mode\n ; ----------------------------------------------------\n mov eax, cr0 ; CR0 \ub808\uc9c0\uc2a4\ud130 \uac12\uc744 \uc77c\ubc18 \ub808\uc9c0\uc2a4\ud130\ub85c \uac00\uc838\uc634\n ; Load the CR0 register value into a general-purpose register.\n\n or eax, 0x00000001 ; 0\ubc88\uc9f8 \ube44\ud2b8(PE: Protection Enable)\ub97c 1\ub85c \uc124\uc815\n ; Set the 0th bit (PE: Protection Enable) to 1.\n mov cr0, eax ; \ubcc0\uacbd\ub41c \uac12\uc744 \ub2e4\uc2dc CR0\uc5d0 \uc801\uc6a9 (\uc774 \uc21c\uac04 32\ube44\ud2b8 \ubaa8\ub4dc \ud65c\uc131\ud654!)\n ; Apply the modified value back to CR0 (32-bit mode is activated at this moment!)\n\n ; ----------------------------------------------------\n ; 4. 32\ube44\ud2b8 \uc138\uadf8\uba3c\ud2b8 \uc601\uc5ed\uc73c\ub85c \uba40\ub9ac\ub6f0\uae30(Far Jump)\n ; 4. Far Jump into 32-bit segment region\n ; ----------------------------------------------------\n ; 0x08\uc740 \uc544\ub798 GDT\uc5d0\uc11c \uc815\uc758\ud55c 32\ube44\ud2b8 \ucf54\ub4dc \uc138\uadf8\uba3c\ud2b8\uc758 \uc704\uce58(\uc624\ud504\uc14b)\uc785\ub2c8\ub2e4.\n ; 0x08 is the offset of the 32-bit code segment defined in the GDT below.\n jmp 0x08:protected_start\n\n\n; ====================================================\n; \uc5ec\uae30\uc11c\ubd80\ud130\ub294 \uc644\uc804\ud788 32\ube44\ud2b8 \uae30\uacc4\uc5b4\ub85c \uc2e4\ud589\ub418\ub294 \uad6c\uc5ed\uc785\ub2c8\ub2e4!\n; From here, the code executes completely in 32-bit machine code!\n; ====================================================\nbits 32\n\nprotected_start:\n ; 32\ube44\ud2b8\uc6a9 \ub370\uc774\ud130 \uc138\uadf8\uba3c\ud2b8 \ub808\uc9c0\uc2a4\ud130\ub4e4 \ucd08\uae30\ud654 (GDT\uc758 0x10 \uc624\ud504\uc14b \uc0ac\uc6a9)\n ; Initialize 32-bit data segment registers (Using 0x10 offset from GDT)\n mov ax, 0x10\n mov ds, ax\n mov es, ax\n mov fs, ax\n mov gs, ax\n mov ss, ax\n\n ; ----------------------------------------------------\n ; 5. [32\ube44\ud2b8 C\uc5b8\uc5b4 \uc2a4\ud0c0\uc77c \ud14c\uc2a4\ud2b8] \ube44\ub514\uc624 \uba54\ubaa8\ub9ac\uc5d0 \uc9c1\uc811 \uc0ac\uac01\ud615 \uadf8\ub9ac\uae30\n ; 5. [32-bit C-style Test] Draw a rectangle directly to Video Memory\n ; ----------------------------------------------------\n ; BIOS\ub97c \ubabb \uc4f0\ubbc0\ub85c \uadf8\ub798\ud53d \ubaa8\ub4dc(VRAM) \uc8fc\uc18c\uc778 0xA0000\uc5d0 \ud3ec\uc778\ud130\ucc98\ub7fc \uc9c1\uc811 \ub370\uc774\ud130\ub97c \uc501\ub2c8\ub2e4.\n ; Since BIOS is unavailable, write data directly to 0xA0000 (VRAM address) like a pointer.\n \n mov edi, 0xA0000 ; \ube44\ub514\uc624 \uba54\ubaa8\ub9ac \uc2dc\uc791 \ubb3c\ub9ac \uc8fc\uc18c\n ; Video memory starting physical address\n\n ; \uac00\ub85c 100, \uc138\ub85c 50 \uc704\uce58 \uacc4\uc0b0: (50 * 320) + 100 = 16100\n ; Calculate position for X=100, Y=50: (50 * 320) + 100 = 16100\n add edi, 16100\n\n mov edx, 0 ; Y \ub8e8\ud504 \uce74\uc6b4\ud130 (\uc138\ub85c 30\uc904)\n ; Y loop counter (30 rows)\n\ndraw_32bit_row:\n mov ecx, 0 ; X \ub8e8\ud504 \uce74\uc6b4\ud130 (\uac00\ub85c 50\uce78)\n ; X loop counter (50 columns)\n\ndraw_32bit_col:\n mov byte [edi], 12 ; \uc0c9\uc0c1 \ubc88\ud638 \ub300\uc785 (12 = \ube68\uac04\uc0c9)\n ; Assign color number (12 = Red)\n inc edi ; \ub2e4\uc74c \ud53d\uc140 \uc8fc\uc18c\ub85c \uc774\ub3d9\n ; Move to the next pixel address\n inc ecx\n cmp ecx, 50\n jl draw_32bit_col\n\n ; \uac00\ub85c \ud55c \uc904\uc744 \ub2e4 \uadf8\ub838\uc73c\uba74, \ub2e4\uc74c \uc904\uc758 \uc2dc\uc791\uc810\uc73c\ub85c EDI \ud3ec\uc778\ud130 \uac74\ub108\ub6f0\uae30\n ; After drawing one row, skip EDI pointer to the start of the next row\n ; \ud55c \uc904\uc774 320\ud53d\uc140\uc778\ub370 \ubc29\uae08 50\ud53d\uc140\uc744 \uc804\uc9c4\ud588\uc73c\ubbc0\ub85c, \ub0a8\uc740 270\ud53d\uc140\ub9cc\ud07c \ub354\ud574\uc90d\ub2c8\ub2e4.\n ; Since a single line is 320 pixels and we have just advanced 50 pixels, we add the remaining 270 pixels.\n add edi, 270\n \n inc edx\n cmp edx, 30\n jl draw_32bit_row\n\n ; \uc791\uc5c5 \uc644\ub8cc \ud6c4 \ubb34\ud55c \ub300\uae30\n ; Infinite loop after work completion\n jmp $\n\n\n; ----------------------------------------------------\n; \ub370\uc774\ud130 \uc601\uc5ed: GDT(Global Descriptor Table) \uad6c\uc870 \uc815\uc758\n; Data Area: Define GDT (Global Descriptor Table) Structure\n; ----------------------------------------------------\nalign 4\n\ngdt_start:\n ; 1. \ub110 \ub514\uc2a4\ud06c\ub9bd\ud130 (\ud558\ub4dc\uc6e8\uc5b4 \uaddc\uaca9\uc0c1 \ud544\uc218\uc801\uc778 \ube48 \uc2ac\ub86f)\n ; 1. Null Descriptor (Mandatory empty slot by hardware specification)\n dd 0, 0 \n\n ; 2. \ucf54\ub4dc \uc138\uadf8\uba3c\ud2b8 \ub514\uc2a4\ud06c\ub9bd\ud130 (\uc624\ud504\uc14b 0x08): \uc804\uccb4 4GB \uc601\uc5ed, \uc77d\uae30\/\uc2e4\ud589 \uac00\ub2a5\n ; 2. Code Segment Descriptor (Offset 0x08): Full 4GB range, Read\/Execute allowed\n dw 0xFFFF, 0x0000\n db 0x00, 0x9A, 0xCF, 0x00\n\n ; 3. \ub370\uc774\ud130 \uc138\uadf8\uba3c\ud2b8 \ub514\uc2a4\ud06c\ub9bd\ud130 (\uc624\ud504\uc14b 0x10): \uc804\uccb4 4GB \uc601\uc5ed, \uc77d\uae30\/\uc4f0\uae30 \uac00\ub2a5\n ; 3. Data Segment Descriptor (Offset 0x10): Full 4GB range, Read\/Write allowed\n dw 0xFFFF, 0x0000\n db 0x00, 0x92, 0xCF, 0x00\ngdt_end:\n\n; CPU\uc5d0 GDT \uc704\uce58\ub97c \uc804\ub2ec\ud558\uae30 \uc704\ud55c \ud3ec\uc778\ud130 \uad6c\uc870\uccb4 (6\ubc14\uc774\ud2b8 \ud06c\uae30)\n; Pointer structure to deliver GDT position to CPU (6 bytes size)\ngdt_pointer:\n dw gdt_end - gdt_start - 1 ; GDT\uc758 \ud06c\uae30 (Size of GDT)\n dd gdt_start ; GDT\uc758 \uc2dc\uc791 \uc8fc\uc18c (Starting address of GDT)\n\n; 512\ubc14\uc774\ud2b8 \ud06c\uae30 \ub9de\ucd94\uae30\n; Pad to 512 bytes\ntimes 512 - ($ - $$) db 0\n<\/code><\/pre>\n\n\n\n
\u2714\ufe0f 1MB \uc774\uc0c1\uc758 \uc0c1\uc704 \uba54\ubaa8\ub9ac \uc601\uc5ed(System Memory)\uc744 \uc0ac\uc6a9\ud558\uae30 \uc704\ud574 ‘A20 \uac8c\uc774\ud2b8(A20 Gate)’\ub77c\ub294 \ud558\ub4dc\uc6e8\uc5b4 \ube57\uc7a5\uc744 \ud478\ub294 \ucf54\ub4dc\uc785\ub2c8\ub2e4. This is code that unlocks the hardware mechanism known as the ‘A20 Gate’ to enable the use of memory areas (system memory) above the 1MB mark.<\/p>\n\n\n\n
in al, 0x92\n or al, 2\n out 0x92, al<\/code><\/pre>\n\n\n\n
— \uc774 \uc124\uc815\uc73c\ub85c 1MB\uc774\uc0c1 \uba54\ubaa8\ub9ac\ub97c \uc0ac\uc6a9\ud560 \uc218 \uc788\uc2b5\ub2c8\ub2e4<\/strong>.(\ucd5c\ub300 4\uae30\uac00 \ubc14\uc774\ud2b8\uae4c\uc9c0 \uc0ac\uc6a9\uac00\ub2a5) With this setting, you can use more than 1 MB of memory<\/strong> (up to a maximum of 4 GB).<\/p>\n\n\n\n
— 32\ube44\ud2b8 \ubcf4\ud638 \ubaa8\ub4dc\uc5d0\uc11c \uc0ac\uc6a9\ud560 \uc218 \uc788\ub294 \ucd5c\ub300 \uba54\ubaa8\ub9ac\uac00 4\uae30\uac00\ubc14\uc774\ud2b8(4GB)\uc778 \uc774\uc720\ub294, 32\ube44\ud2b8 CPU\uac00 \ud55c \ubc88\uc5d0 \uac00\ub9ac\ud0ac \uc218 \uc788\ub294 \ubc29 \ubc88\ud638(\uba54\ubaa8\ub9ac \uc8fc\uc18c)\uc758 \ucd1d\uac1c\uc218\uac00 \ub531 4,294,967,296\uac1c\uc774\uae30 \ub54c\ubb38\uc785\ub2c8\ub2e4. The reason the maximum memory available in 32-bit protected mode is 4 gigabytes (4GB) is that the total number of room numbers (memory addresses) a 32-bit CPU can reference at once is exactly 4,294,967,296.<\/p>\n\n\n\n
— in al, 0x92 \uc2dc\uc2a4\ud15c \uc81c\uc5b4 \ud3ec\ud2b8(0x92)\uc5d0\uc11c \ud604\uc7ac \uc124\uc815 \uc0c1\ud0dc\ub97c 1\ubc14\uc774\ud2b8 \uc77d\uc5b4 AL \ub808\uc9c0\uc2a4\ud130\uc5d0 \uc800\uc7a5\ud569\ub2c8\ub2e4. Read the current setting status (1 byte) from system control port 0x92 and store it in the AL register.<\/p>\n\n\n\n
— or al, 2 AL \ub808\uc9c0\uc2a4\ud130\uc758 \uac12 \uc911 ‘2\ubc88\uc9f8 \ube44\ud2b8'(\uc774\uc9c4\uc218\ub85c 00000010)\ub97c 1\ub85c \uac15\uc81c \uc804\ud658\ud569\ub2c8\ub2e4. Force the ‘second bit’ (00000010 in binary) of the AL register’s value to 1.<\/p>\n\n\n\n
1) al\uacfc 2\uc758\uac12\uc744 or\uc5f0\uc0b0 \ud569\ub2c8\ub2e4.(\uc608) Perform an OR operation on the values \u200b\u200bof AL and 2. (Example)<\/p>\n\n\n\n
— out 0x92, al \ubcc0\uacbd\ub41c \uc124\uc815 \uac12\uc744 \ub2e4\uc2dc \ud3ec\ud2b8 0x92\uc5d0 \ubcf4\ub0b4\uc11c \ud558\ub4dc\uc6e8\uc5b4\uc5d0 \uc801\uc6a9\ud569\ub2c8\ub2e4. The modified setting values \u200b\u200bare sent back to port 0x92 to apply them to the hardware.<\/p>\n\n\n\n
out 0x92, al<\/code><\/pre>\n\n\n\n
\u2714\ufe0f GDT(Global Descriptor Table) \uc815\ubcf4\ub97c CPU\uc5d0 \ub85c\ub4dc Load GDT (Global Descriptor Table) information into CPU<\/p>\n\n\n\n
cli ; 32\ube44\ud2b8 \uc804\ud658 \uc911 \ubc29\ud574\ubc1b\uc9c0 \uc54a\ub3c4\ub85d \ud558\ub4dc\uc6e8\uc5b4 \uc778\ud130\ub7fd\ud2b8 \uae08\uc9c0\n ; Disable hardware interrupts to avoid interruption during 32-bit transition\n lgdt [gdt_pointer] ; GDT \uad6c\uc870\uccb4\uc758 \uc8fc\uc18c\ub97c CPU\uc5d0 \ub85c\ub4dc\n ; Load the address of the GDT structure into the CPU<\/code><\/pre>\n\n\n\n
— cli : Clear Interrupt Flag CPU\uac00 \ud558\ub4dc\uc6e8\uc5b4 \uc778\ud130\ub7fd\ud2b8\ub97c \ubc1b\uc9c0 \uc54a\ub3c4\ub85d \uc124\uc815\ud558\ub294 \uba85\ub839\uc785\ub2c8\ub2e4. This is a command that configures the CPU not to accept hardware interrupts.<\/p>\n\n\n\n
2)\uc138\uadf8\uba3c\ud2b8 \ub808\uc9c0\uc2a4\ud130(CS, DS, SS \ub4f1)\ub294 \uc774 GDT\ub97c \uae30\uc900\uc73c\ub85c \ud574\uc11d\ub77c\uace0 \uc54c\ub824\uc8fc\ub294 \uac83\uc785\ub2c8\ub2e4. Segment registers (such as CS, DS, and SS) are configured to be interpreted based on this GDT.<\/p>\n\n\n\n
\u2714\ufe0f CR0 \ub808\uc9c0\uc2a4\ud130\ub97c \uc124\uc815\ud558\uc5ec 32\ube44\ud2b8 \ubcf4\ud638 \ubaa8\ub4dc \ud65c\uc131\ud654 Set CR0 register to enable 32-bit Protected Mode<\/p>\n\n\n\n
— CS(Code Segment) : \uae30\uacc4\uc5b4\uac00 \uc800\uc7a5\ub41c \uba54\ubaa8\ub9ac\uc758 \uc704\uce58\ub97c \ucc3e\ub294 \ub370 \uc0ac\uc6a9\ub418\ub294 \ub808\uc9c0\uc2a4\ud130 A register used to locate the memory address where machine code is stored.<\/p>\n\n\n\n
— cr0\uc5d0 \uc9c1\uc811 \uac12\uc744 \uc785\ub825 \ud560 \uc218 \uc5c6\uc2b5\ub2c8\ub2e4. You cannot directly assign a value to cr0.<\/p>\n\n\n\n
— cr0\ub294 \uc81c\uc5b4\ub808\uc9c0\uc2a4\ud2b8\ub85c \ub2e4\ub978 \ube44\ud2b8\ub4e4\uc774 \ub4e4\uc5b4 \uc788\uae30 \ub54c\ubb38\uc5d0 \uae30\uc874 \uac12\uc744 \uc77d\uc5b4\uc640\uc11c 0\ubc88\uc9f8 \ube44\ud2b8 (PE:Protection Enable)\uac12\ub9cc \ubc14\uafc9\ub2c8\ub2e4. Since cr0 is a control register containing other bits, you must read the existing value and modify only the 0th bit (PE: Protection Enable).<\/p>\n\n\n\n
mov eax, cr0 ; CR0 \ub808\uc9c0\uc2a4\ud130 \uac12\uc744 \uc77c\ubc18 \ub808\uc9c0\uc2a4\ud130\ub85c \uac00\uc838\uc634\n ; Load the CR0 register value into a general-purpose register.\n\n or eax, 0x00000001 ; 0\ubc88\uc9f8 \ube44\ud2b8(PE: Protection Enable)\ub97c 1\ub85c \uc124\uc815\n ; Set the 0th bit (PE: Protection Enable) to 1.\n mov cr0, eax ; \ubcc0\uacbd\ub41c \uac12\uc744 \ub2e4\uc2dc CR0\uc5d0 \uc801\uc6a9 (\uc774 \uc21c\uac04 32\ube44\ud2b8 \ubaa8\ub4dc \ud65c\uc131\ud654!)\n ; Apply the modified value back to CR0 (32-bit mode is activated at this moment!)<\/code><\/pre>\n\n\n\n
\u2714\ufe0f protected_start\ub77c\ubca8\ub85c far jump\ud569\ub2c8\ub2e4. Perform a far jump to protected_start<\/code>.<\/p>\n\n\n\n
jmp 0x08:protected_start<\/code><\/pre>\n\n\n\n
— BIOS(\ub9ac\uc5bc \ubaa8\ub4dc)\uc5d0\uc11c \uc0ac\uc6a9\ud558\ub358 \uc138\uadf8\uba3c\ud2b8 \uc8fc\uc18c \uacc4\uc0b0 \ubc29\uc2dd\uc774 \ubcf4\ud638 \ubaa8\ub4dc\uc5d0\uc11c\ub294 \ub354 \uc774\uc0c1 \uc0ac\uc6a9\ub418\uc9c0 \uc54a\uae30 \ub54c\ubb38\uc5d0, CPU\uac00 \uc0ac\uc6a9\ud560 \uc0c8\ub85c\uc6b4 \uc138\uadf8\uba3c\ud2b8 \uc815\ubcf4(GDT)\ub97c lgdt\ub85c \ub4f1\ub85d\ud569\ub2c8\ub2e4. Since the segment address calculation method used in BIOS (real mode) is no longer employed in protected mode, the lgdt<\/code> instruction is used to register the new segment information (GDT) for the CPU.<\/p>\n\n\n\n
— 0x08\ub294 \ub9ac\uc5bc\ubaa8\ub4dc\uc5d0\uc11c \uc0ac\uc6a9\ud558\ub358 cs\uac12\uc744 GDT\uc758 \uc120\ud0dd\uc790\ub85c \ubc14\uafc9\ub2c8\ub2e4. 0x08 replaces the CS value used in real mode with a GDT selector.<\/p>\n\n\n\n
— 0x08\ub294\ub354 \uc774\uc0c1 \uc8fc\uc18c \uac12\uc774 \uc544\ub2cc GDT\uc758 \uc120\ud0dd\uc790\uac00 \ub429\ub2c8\ub2e4. 0x08 is no longer an address value but becomes a GDT selector.<\/p>\n\n\n\n
— \ub9ac\uc5bc\ubaa8\ub4dc(16\ube44\ud2b8) : CS = \uc2e4\uc81c \uc138\uadf8\uba3c\ud2b8 \uc8fc\uc18c Real Mode (16-bit): CS = Actual segment address<\/p>\n\n\n\n
— \ubcf4\ud638\ubaa8\ub4dc(32\ube44\ud2b8) : CS = GDT\uc758 \ucf54\ub4dc \uc138\uadf8\uba3c\ud2b8 \uc120\ud0dd\uc790 Protected Mode (32-bit): CS = Code segment selector from the GDT<\/p>\n\n\n\n
— GDT\uc758 \uad6c\uc870 Structure of the GDT<\/p>\n\n\n\n
\ud83d\udc49\ufe0f 32\ube44\ud2b8 \ubcf4\ud638\ubaa8\ub4dc\ub85c \uc804\ud658\ud558\ub294 \ubd80\ubd84\uc785\ub2c8\ub2e4.This is the part where the system switches to 32-bit protected mode. \ud83d\udc49\ufe0f 16\ube44\ud2b8\uc5d0\uc11c \uadf8\ub798\ud53d \ubaa8\ub4dc\ub85c \uc124\uc815\ud558\uace0 32\ube44\ud2b8 \ubcf4\ud638\ubaa8\ub4dc\ub85c \uc804\ud658\ud6c4\uc5d0 \ud654\uba74\uc5d0 \ud551\ud06c\uc0c9 \uc0ac\uac01\ud615\uc744 \uadf8\ub9ac\ub294 \ucf54\ub4dc\uc785\ub2c8\ub2e4.This code sets the system to 16-bit graphics mode, switches to 32-bit protected mode, and then draws a pink rectangle on the screen. \ud83d\udc49\ufe0f \uc804\uccb4 \ucf54\ub4dc \/ […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[26,1],"tags":[],"class_list":["post-6092","post","type-post","status-publish","format-standard","hentry","category-os","category-uncategorized","missing-thumbnail"],"_links":{"self":[{"href":"https:\/\/www.freelifemakers.org\/wordpress\/index.php\/wp-json\/wp\/v2\/posts\/6092","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.freelifemakers.org\/wordpress\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.freelifemakers.org\/wordpress\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.freelifemakers.org\/wordpress\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.freelifemakers.org\/wordpress\/index.php\/wp-json\/wp\/v2\/comments?post=6092"}],"version-history":[{"count":8,"href":"https:\/\/www.freelifemakers.org\/wordpress\/index.php\/wp-json\/wp\/v2\/posts\/6092\/revisions"}],"predecessor-version":[{"id":6102,"href":"https:\/\/www.freelifemakers.org\/wordpress\/index.php\/wp-json\/wp\/v2\/posts\/6092\/revisions\/6102"}],"wp:attachment":[{"href":"https:\/\/www.freelifemakers.org\/wordpress\/index.php\/wp-json\/wp\/v2\/media?parent=6092"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.freelifemakers.org\/wordpress\/index.php\/wp-json\/wp\/v2\/categories?post=6092"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.freelifemakers.org\/wordpress\/index.php\/wp-json\/wp\/v2\/tags?post=6092"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
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<\/figure>\n\n\n\n